What you will be working on

• Ensuring 1st time yielding silicon, benchmark D0 for baseline and products.
• Identify & resolve Product, Test & Fab-Process related yield limiters in shortest time possible.
• Technical interface with Business Lines/customers
• Driver for yield improvement
• Resolve product yield, quality and reliability issues
• Perform pre-tapeout risk assessment and communicate with Business line/Fab on the necessary actions to eliminate/minimize the risk.
• Work with Customers/Mother Fab on the DfM related issue.
• Conduct product yield analyses to identify root cause of wafer sort and final test failures
• Set up fault diagnostic capabilities for yield improvement
• Work with Business line/customers on product low yield disposition
• Perform electrical and physical failure analysis to isolate fail location
• Drive the yield improvement task force

More about you

• Master/bachelor’s degree in electrical / Electronic Engineering or Science in Physics
• 2 – 8 years product and/or test engineering, failure analysis or process-integration experience
• Experience in Fab process, yield engineering or design will be an added advantage
• In depth knowledge of semiconductor device physics, electrical & electronics engineering fundamentals & wafer fabrication processes
• Strong analytical & problem-solving skills
• Good interpersonal and communication skills